Electrothermal Modeling of Carbon Nanotube-Based TSVs

Three-dimensional integrated circuits (3-D ICs) have attracted much interest in the past one decade because they can achieve technically breakthrough and significant enhancement in their electrical performance in comparison with that of conventional two-dimensional ICs. As the key technique for realization of ultra-high density integration and miniaturized packaging of 3-D ICs, through-silicon via (TSV) provides vertical electrical connection between different functional chips through multilayered silicon dies [1–3]. Moreover, it offers an opportunity for heterogeneously flexible integration, which is a powerful and effective solution called as “More-than-Moore” technology. Till now, there are numerous papers published on modeling, characterizing, and fabricating many different TSV structures for development of various 3-D ICs [4–13]. The most common TSV filling materials currently being used are copper (Cu), tungsten (W), and even doped poly-silicon. However, there are still some reliability and thermal management issues to be further studied in the realization of TSV-based 3-D ICs.